1. Field of the Invention
This invention pertains to a communications system utilizing ATM (Asynchronous Transmission Mode) cells, and more particularly to a virtual identifier (VPI/VCI) conversion system in a virtual channel converter (VCC) provided before an ATM cell switcher. The virtual identifier (VPI/VCI) conversion system converts a virtual path identifier (VPI) and a virtual channel identifier (VCI) attached to an incoming ATM cell on an input highway of the ATM cell switcher to those to be attached to an outgoing ATM cell on an output highway thereof and attaches a tag comprising information of the ATM cell switching within the ATM cell switcher, before inputting the ATM cell to the switcher.
2. Description of the Related Art
A Broadband Integrated Services Digital Network (B-ISDN) transmits cells in a packet form having a fixed length. Such cells are called ATM cells. The header parts of these cells have a virtual path identifier (VPI) and a virtual channel identifier (VCI), which identify the cell destination and so forth.
FIG. 1 is a block diagram of an ATM cell switching system
A virtual channel converter (VCC) 1 receives an incoming ATM cell transmitted to the ATM cell switching system from one of its input highways, converts the virtual identifiers (VPI/VCI) in the ATM cell, and attaches a tag to the ATM cell for its switching within the switcher. More specifically, the VCC 1 converts the VPI and VCI in the header part of an incoming ATM cell on an input highway to those of an outgoing ATM cell on an output highway, and also adds the tag for its switching control.
A multiplexer (MUX) 2 multiplexes an ATM cell outputted from the VCC 1. Switching modules 3, 4 and 5 in the first, second and third stages of a switcher switch the multiplexed ATM cell. A demultiplexer (DMX) 6 demultiplexes and outputs the multiplexed ATM cell to one of plural output highways. Here, the switching modules 3, 4 and 5 are generally called self-routing modules (SRMs). The SRM in a particular stage switches an ATM cell according to the content of the tag attached by the VCC 1. Thus, the switching modules 3, 4 and 5 together switch the ATM cell finally to the destined one of the plural output highways.
FIG. 2 shows an ATM cell format.
An ATM cell comprises five (5) bytes of a header part for storing its VPI and VCI and forty-eight (48) bytes of an information field for storing data to be transmitted.
The content in the five (5) bytes of the header part for a UNI cell transmitted between a user and a network is slightly different from that for an NNI cell transmitted between networks. Although a UNI cell includes four (4) bits for indicating a general flow control (GFC) used by a user terminal as shown in FIG. 2, an NNI cell does not include four (4) GFC bits.
After the four (4) GFC bits (or in their absence), the header part contains the VPI and VCI of the ATM cell, four (4) bits for specifying a payload type (PT), and eight (8) bits for a header error control (HEC) used in correcting a header error. Therefore, a UNI cell has twenty-four (24) bits of a VPI/VCI, whereas an NNI cell has twenty-eight (28) bits of VPI/VCI.
FIG. 3 is a block diagram of a conventional virtual channel converter (VCC).
A call processor (CPR) 7 controls the switching of all the ATM cells. An order taker/server 8 controls the communications path according to a command from the CPR 7. An input VPI/VCI register 9 and a header inserter 10 receive an incoming ATM cell from an input highway (IHW).
Then, an input VPI/VCI register 9 supplies the input VPI/VCI in a maximum of twenty-eight (28) bits to a conversion table random access memory (RAM) 13, as its read address, at timings generated by a timing generator (TG) 11.
The conversion table RAM 13 stores, according to an advance command from the CPR 7 through the order taker/server 8, the VPI/VCI of an outgoing ATM cell in correspondence with the VPI/VCI of an incoming ATM cell and a tag giving information necessary for routing the ATM cell in the switching modules 3, 4 and 5, (which are SRMs,) and the demultiplexer 6. The conversion table RAM 13 outputs the storage content corresponding to the input VPI/VCI to the header inserter 10.
Here, it is assumed that the SRM in a particular stage, i.e. one of the switching modules 3, 4 and 5, and the demultiplexer 6 require four (4) bits each, i.e. sixteen (16) bits in total, for routing an ATM cell. These sixteen (16) bits compose the tag, which is added before the VPI/VCI in a maximum of twenty-eight (28) bits. Thus, the conversion table RAM 13 outputs forty-four (44) bits. The header inserter 10 attaches the content to the ATM cell before the switcher receives it.
As explained by referring to FIG. 3, because the conversion table RAM 13 stores the conversion information for VPI/VCI and tag information for routing an ATM cell within the switcher, the conversion table RAM 13 must have 2.sup.28, i.e. about two hundred sixty million (260,000,000), addresses. The current art can not easily convert an input VPI/VCI having twenty-eight (28) bits to forty-four (44) bits including also tag information, because of problems in hardware amount and access speed.
Thus, instead of supporting all twenty-eight (28) bits composing the VPI/VCI, the conventional art compresses the twenty-eight (28) bits to eight (8) bits, thereby constructing a conversion table RAM 13 comprising 2.sup.8, i.e. two hundred fifty-six (256), addresses. Although this is technically possible, its general use is impossible, because compatibility with the conversion table RAMs of other models must be sacrificed.
That is, when only eight (8) of the twenty-eight (28) bits are supported, the problem arises which eight (8) bits out of the twenty-eight (28) bits are to be used. For instance, a model using the eight (8) least significant bits (LSB) is not compatible with another using the eight (8) most significant bits (MSB).